BASSAM JAMIL RASHEED MOHD

Bassam Jamil Rasheed Mohammed	Professor
Electrical and Computer Engineering
Faculty of Engineering	Department of Computer Engineering
Bassam@hu.edu.jo	http://staff.hu.edu.jo/bassam
ORCID ID :
Office No. : E 3056	EXT : 5126

C.V. Document file as PDF:

Ph.D.	University of Texas at Austin	The United States of America,2008
Master	University of Louisiana, Lafayette	The United States of America,1992
Bachelor	KFUPM, Dhahran	Saudi Arabia,1990

 •	DSP VLSI Design
•	FPGA VLSI Design
•	Steganography and Setagonalysis
•	Low Power VLSI Design
•	High-Performance VLSI Circuits

 •	B. Mohd, E. E. Swartzlander, Jr., “A Power-Scalable Switch-Based Multi-Processor FFT,” 20th IEEE International Conference on Application-specific Systems, Architecture and Processors, Boston, July 7-9, 2009.
•	S. Bijansky, B. Mohd and B. Mohammad “ Using ESP-CV for Dynamic Power Analysis of Custom Macros to Reduce Analysis Time and Improve Accuracy”, IEEE International Conference on IC Design & Technology, Austin, TX, May 18-20, 2009
•	S. Bijansky Jr,  B. Mohd, B. Mohammad, “Dynamic Power Analysis For Custom Designs, ”, Qualcomm Technology Conference (QTech)-2009, San Diego, June, 2009.
•	B. Mohd, M. Saint-Laurent, P. Bassett, S. Imam “Reducing Flip-Flop Power for DSP Design,” Third Annual Austin Conference on Integrated Systems and Circuits, pp. 34-39, Austin, TX, May 2008 
•	B. Mohd, A. Aziz and E. E. Swartzlander, Jr. “The hazard-free superscalar pipeline fast Fourier transform algorithm and architecture,” 15th annual IFIP VLSI SoC 2007, pp. 194-199, Atlanta, October 2007.
•	H. Saleh, B. Mohd, A. Aziz and E. E. Swartzlander, Jr. “Contention-free switch-based implementation of 1024-point Fourier transform engine,” 25th IEEE International Conference on Computer Design, pp. 7-12, Lake Tahoe, CA, October 2007.
•	A. Wakefield, B. Mohd, “Constructing Reusable Testbenches” Seventh Annual IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002.
•	B. Mohd, M. Hibarger, B. Chin, J. Chen. “Packet-Data-Path Functional Verification Testbench: Stimulus Generation and User Interface.” Synopsys User Group Conference, Boston, 2002
•	T. Madraswala, B. Mohd, M. Ali, R. Premi, M. Bayoumi, ” A reconfigurable ANN Architecture”, IEEE International Symposium on Circuits and Systems, San Diego, May 1992.

 Assistant Professor, Hashemite University, Zarqa, Jordan (Present)
Active member of the Computer Engineering Department in the Hashemite University. Tasks include:
•	Successfully taught the following courses: digital logic, systems programming, digital integrated circuits and discrete math.
•	Oversaw various laboratory courses.
•	Participated in various committees and task forces.
	
Staff Engineer, Qualcomm, Austin, TX (July, 2005 – August, 2009)
Participated in the design of the Hexagon Digital Signal Processor. Tasks included:
•	Develop object-oriented programs (in Vera language) to construct test-benches for verification.
•	Developed power estimation flow to accurately measure RTL design power. Developed software flow using Perl and Tcl-tk languages. 
•	Performed power analysis to estimate power and identify power optimizations. 

Staff Consultant, Synopsys, Austin, TX (August, 1998 – July, 2005)
As part of the professional consulting services, the mission was to assist our customers to adopt Synopsys software tools. Tasks include:
•	On-site training for our customer to adopt Vera, an object oriented programming language to build testbenches and write tests.
•	Participated in customer projects in writing Vera programs and tests.

Design Engineer, Tundra Semiconductor, Ottawa, ON (July, 1997 – July, 1998)
Designed and verified DMA controller. Participated in place and route physical design tasks.

Design Engineer, Sun Microsystems, Sunnyvale, CA (September, 1995 – June, 1997)
As member of Ultra-Sparc-III team, designed the floating point divider array and performed a detailed study on the circuit noise.

Design Engineer, MasPar Corporation, Sunnyvale, CA (February, 1995 – September, 1995)
Performed timing analysis on the processing element of the MasPar computer. 

Design Engineer, Intel, Hillsboro, OR (September, 1992 – February, 1995)
As a member of the PentiumPro team, designed circuits in execution unit, including shifter, adder and clocks.

 - Embedded Systems
 - Digital Integrated Circuits
 - Computer Organization
 - Systems Programming
 - C++ programming
 - Digital Logic
 - Computer Foundations

BASSAM JAMIL RASHEED MOHD

BASSAM JAMIL RASHEED MOHD

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