| Research Title | MAG. TITLE | RESEARCH AREA | PUBLISH YEAR | DOI | Journal URL |
| Automatic Verification of Reduction Techniques in Higher Order Logic | Formal Aspects of Computing, Springer London | Verification | 2013 | |
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| Hierarchical Steganography Using Novel Optimum Quantization Technique | Signal, Image and Video Processing, Springer-Verlag London | VLSI and Image Processing | 2013 | |
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| A Novel Approach to Enhance Distributed Virtual Memory | Computers and Electrical Engineering, Elsevier | Computer Architecture: Distributed Virtual Memory | 2012 | |
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| Carry-Based Reduction Parallel Counter Design | International Journal of Electronics, Taylor & Francis, London, UK | VLSI | 2012 | |
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| MDG-SAT: an automated methodology for efficient safety checking | International Journal of Critical Computer-Based Systems (IJCCBS), Inderscience Publishers | Formal Methods, Verification | 2012 | |
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| NuMDG: A New Tool for Multiway Decision Graphs Construction | Journal of Computer Science and Technology (JCST), Springer, Institute of Computing Technology, Science Press | Formal Verification | 2011 | |
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| LCF-style Platform based on Multiway Decision Graphs | Electronic Notes in Theoretical Computer Science (ENTCS), Elsevier | Formal Methods, Verification | 2009 | |
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| Towards a Reachability Approach by Combining HOL Induction and Multiway Decision Graphs | Journal of Computer Science and Technology (JCST), Springer Boston | Formal Methods | 2009 | |
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| On the Integration of Decision Diagrams in High Order Logic based Theorem Provers: a Survey | Journal of Computer Science, Science Publication | Formal Methods | 2007 | |
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| Closed-Loop Control System Robustness Improvement by Parameterized State Feedback | IEE Proc.- Control Theory Appl. | Control System | 1998 | |
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