عوني حسين علي اطرادات استاذ هندسة الحاسوب هندسة الحاسوب كلية الهندسة قسم هندسة الحاسوب itradat@hu.edu.jo http://staff.hu.edu.jo/awni رقم الاوركيد:   رقم المكتب: 3059 الفرعي : 4828

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الدكتوراه Concordia University كندا,2009 الماجستير Concordia University كندا,2004 البكالوريس جامعة العلوم والتكنولوجيا الاردن,2000               General research areas are high-level synthesis and parallel architectures. Research interests include scheduling and resource allocation, reconfigurable computing, ASIC synthesis, graph theory, Network on chip, Networks and information security and computer architecture and organization.           1. A. Itradat, M.O. Ahmad, A. Shatnawi, “High-level Architectural Synthesis of DSP Data Flow Graphs with Inter-Processor Communication Delays,” Accepted for publication IET Journal on Circuits, Devices. 2. A. Itradat, M.O. Ahmad, A. Shatnawi, “Interconnect-Aware Register Binding with and without Node Regeneration for High-Level Synthesis,” Accepted with Minor revision for possible publication In IEEE Transaction on Computer Aided Design for Integrated Circuits and Systems. 3. A. Itradat, M.O. Ahmad, A. Shatnawi, “Incorporating of Reconfigurable units in a Simultaneous Scheduling, Allocation, and Placement with Interprocessor Communication Delay,” Submitted for possible publication in IEEE Transaction on Computer Aided Design for Integrated Circuits and Systems. 4. A. Itradat, M.O. Ahmad, A. Shatnawi, “Delay and sampling-rate aware architectural synthesis in presence of communication overhead,” In The 3rd International IEEE-NEWCAS 2008 Conference, Quebec, Canada, 22-25 June 2008, Page(s): 323 – 326. 5. A. Itradat, M.O. Ahmad, A. Shatnawi, “Minimization of I/O delay in the architectural synthesis of DSP data flow graphs,” in the IEEE International Symposium on Circuits and Systems. ISCAS 2008, Seattle, USA, May 18-21, 2008, pp. 205 - 208. 6. A. Itradat, M.O. Ahmad, A. Shatnawi, “Architectural synthesis of DSP applications with dynamically reconfigurable functional units,” In the IEEE International Symposium on Circuits and Systems. ISCAS 2007, New Orleans, USA, 27-30 May 2007, Page(s):1037 - 1040. 7. A. Itradat, M.O. Ahmad, A. Shatnawi, “Dynamically reconfigurable adaptable multi-module based synthesis of DSP data flow graphs,” In IEEE Canadian Conference on Electrical and Computer Engineering 2007, CCECE 2007, Vancouver, Canada, 22-26 April 2007, Page(s):1515 – 1518. 8. A. Itradat, M.O. Ahmad, A. Shatnawi, “A processor allocation of DSP applications onto heterogeneous multiprocessor architectures,” In IEEE Canadian Conference on Electrical and Computer Engineering 2007, CCECE 2007, Vancouver, Canada, 22-26 April 2007 Page(s):944 - 947. 9. A. Itradat, M.O. Ahmad, A. Shatnawi, “A delay-optimal static scheduling of DSP applications mapped onto multiprocessor architectures,” In the IEEE International Symposium on Parallel Computing in Electrical Engineering 2006, PARELEC 2006., Bialystok, Poland, 13-17 Sept. 2006, Page(s):386 – 391. 10. A. Itradat, M.O. Ahmad, A. Shatnawi, “Incorporation of reservation stations into the scheduling of DSP graphs onto heterogeneous multiprocessors,” In IEEE 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, 7-10 Aug. 2005, Cincinnati, USA, Vol. 1, Page(s):460 - 463. 11. A. Itradat, M.O. Ahmad, A. Shatnawi, “Scheduling of DSP algorithms onto heterogeneous multiprocessors with inter-processor communication,” In The 3rd International IEEE-NEWCAS 2005 Conference, Quebec, Canada, 19-22 June 2005, Page(s):95 – 98. 12. A. Itradat, M.O. Ahmad, A. Shatnawi, “Scheduling of DSP data flow graphs with processing times characterized by fuzzy sets,” In Canadian Conference on Electrical and Computer Engineering 2004 , IEEE CCECE 2004, Niagara Falls, Canada, 2-5 May 2004, Vol. 3, Page(s):1245 – 1248.                   -           -          -            -